Implementing electric circuits involves connecting isolated circuit components or devices through specific electrical paths. When fabricating integrated circuits into a semiconductor substrate, it is necessary to electrically isolate devices within the substrate from other devices within the substrate. The devices are subsequently interconnected to create specific desired circuit configurations.
Typically the first several steps in semiconductor device processing involve dividing the wafer into active regions, or source/drain regions, where transistors will be formed and field regions that isolate adjacent active areas. In general, semiconductor devices, or integrated circuits (ICs), have utilized either trench isolation or selective oxidation such as local oxidation of silicon (LOCOS) to electrically insulate or isolate various portions of the semiconductor device from other portions of the device. Trench isolation typically involves etching a recess or trench in the silicon (Si) substrate, filling the trench with an insulation material such as silicon oxide by using, for example, tetraethylorthosilicate (TEOS), and planarizing the insulation material. LOCOS techniques typically involve growing a pad or liner oxide on a Si substrate, depositing a nitride film, patterning and etching the nitride film and then growing or forming an oxide and heating the substrate so that the exposed portions of the oxide grow to form an insulating medium in the semiconductor device.
The isolation regions for semiconductor devices vary in size depending on parameters or requirements necessary for proper electrical isolation and charge carrier isolation in the device. For example, in complementary metal oxide semiconductor (CMOS) devices including integrated circuits (ICs) such as logic and memory components, both wide isolation regions and narrow isolation regions are necessary on the Si substrate to effectively isolate certain areas of the semiconductor chip or device. Certain areas of the semiconductor chip require large isolation regions while others require small isolation regions due to different voltage requirements, dopant types, increased circuit packing density, dopant concentrations, or other criteria associated with IC design.
As various semiconductor devices or ICs have become smaller, the demands for the efficient use of space by isolation regions has increased. The use of trench isolation regions has helped satisfy these demands due to their relatively small size. However, trench isolation regions are susceptible to unevenness or "dishing" when the trench isolation regions are planarized. Dishing is a particular problem when wide and narrow isolation regions are employed in the semiconductor device because the insulating material (e.g., TEOS) tends to be removed from the wide isolation regions more quickly than from the narrow isolation regions. Conventional LOCOS techniques can be disadvantageous because they require relatively large lateral spacing on the semiconductor substrate.
A conventional method of trench isolation formation is depicted in FIGS. 1A-1H. A pad oxide layer 111 is thermally grown on the surface of a silicon substrate 110 having well regions 130 and 140 as depicted in FIG. 1A. Next, a layer of silicon nitride 112 is deposited by chemical vapor deposition (CVD) on top of the pad oxide layer 111 as depicted in FIG. 1B. A photo-resist mask layer 115 depicted in FIG. 1C is then deposited and patterned on top of the nitride layer 112. A dry etch is performed to etch nitride, oxide and to form Si trenches in the open regions 114, as depicted by 161-163 in FIG. 1D after the resist 115 is removed.
After the trench formation, an oxide layer 150 of a thickness H, where H is greater than the thickness of the nitride layer 112 plus the thickness of the pad oxide layer 111 plus the height of the trench 162, is deposited by CVD above the remaining portions of the nitride layer 112 and the trenches 161-163. Basically, the main criteria is to make sure that the level of the CVD oxide layer 150 is above the level of the nitride layer 112, as depicted in FIG. 1E.
The step of depositing the CVD oxide layer 150 is followed by a planarization technique. Planarization is carried out by the use of a planarization mask 151 as depicted in FIG. 1F. After the planarization mask 151 is applied, the CVD oxide layer 150 is etched and the planarization mask 151 is removed. The resulting structure is illustrated in FIG. 1G. The structure of FIG. 1G is then polished to yield the structure of FIG. 1H, which shows that the level of the oxide 150 at the center portions of the trenches 161-163 are lower in height than at the edge portions of the trenches 161-163. This phenomenon is known in the art as "dishing" and adversely affects the planarity of the IC.
It has been demonstrated that by limiting the width of the isolation trenches separating active regions, the dishing effect can be minimized. For example, U.S. Pat. No. 5,742,090, issued on Apr. 21, 1998, to Andre Stolmeijer et al describes such an IC. FIGS. 2A-2E illustrate the steps of preparing the isolation structure according to the invention described in Stolmeijer et al. A pad oxide layer 11 is thermally grown on the surface of a silicon substrate 10 having well regions 30 and 40 as depicted in FIG. 2A. Next, a layer of CVD silicon nitride 12 is deposited on top of the pad oxide layer 11 as depicted in FIG. 2B. A photo-resist mask layer (not shown) is then deposited on top of the nitride layer 12 and the region of the nitride layer 12 exposed through the mask layer is anistropically dry etched to produce etched openings 14 (preferably all of equal limited width) through the nitride layer 12 (see FIG. 2C). The etched openings define regions that are subsequently etched to form isolation trenches 71-75 illustrated in FIG. 2D. The etched openings 14 are controlled to be preferably less than or equal to about 0.5 .mu.m. Alternatively, trenches can be formed by etching nitride, oxide and forming an Si trench without relying on nitride as an etch mask.
After the trench formation, an oxide layer is deposited above the remaining portions of the nitride layer 12 and the trenches 71-75, and is polished until the entire upper surface of the remaining portions of the nitride is exposed. The resulting structure after the step of polishing is illustrated in FIG. 2E, which shows that because of the limited width of the trenches 71-75, the level of the oxide in the center portions of the trenches 71-75 are substantially the same as the level of the oxide at the edge portions of the trenches 71-75. In other words, dishing has been minimized. The use of limited width isolation trenches completely eliminates the costly steps of using a planarization mask, etching the CVD oxide layer, and removing the planarization mask.
The use of limited width isolation trenches provides a cost-effective way to electrically isolate devices within the substrate from other devices within the substrate. However, as ICs become smaller and more complex the concern becomes how to effectively generate a mask needed to create such narrow isolation trenches. The patent to Stolmeijer et al. did not account for field poly connection and local interconnect (LI) where isolations are needed. Thus there is a need for a method for effectively generating limited trench width isolation structures to satisfy isolation requirement of more complex layout situations. There is also a need for a method of fabricating a semiconductor device having isolation regions formed by a space efficient process that is not susceptible to dishing problems.